<?xml version="1.0" encoding="UTF-8"?>
<doi_batch version="5.4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://www.crossref.org/schema/5.4.0" xsi:schemaLocation="http://www.crossref.org/schema/5.4.0 https://www.crossref.org/schemas/crossref5.4.0.xsd" xmlns:jats="http://www.ncbi.nlm.nih.gov/JATS1" xmlns:fr="http://www.crossref.org/fundref.xsd" xmlns:ai="http://www.crossref.org/AccessIndicators.xsd" xmlns:rel="http://www.crossref.org/relations.xsd" xmlns:mml="http://www.w3.org/1998/Math/MathML">
  <head>
    <doi_batch_id>NONE</doi_batch_id>
    <timestamp>20251231120729876</timestamp>
    <depositor>
      <depositor_name>wseas/wseas</depositor_name>
      <email_address>content-registration-form+ja@crossref.org</email_address>
    </depositor>
    <registrant>content-registration-form</registrant>
  </head>
  <body>
    <journal>
      <journal_metadata>
        <full_title>WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS</full_title>
        <issn media_type="print">1109-2734</issn>
        <issn media_type="electronic">2224-266X</issn>
      </journal_metadata>
      <journal_article>
        <titles>
          <title>Asynchronous Digital System Architecture and FPGA Implementation</title>
        </titles>
        <contributors>
          <person_name sequence="first" contributor_role="author">
            <given_name>Grigore Mihai</given_name>
            <surname>Timis</surname>
            <affiliations>
              <institution>
                <institution_name>Technical University “Gh.Asachi”Iasi, Faculty of Automatic Control and Computer Engineering, ROMANIA</institution_name>
              </institution>
            </affiliations>
          </person_name>
          <person_name sequence="additional" contributor_role="author">
            <given_name>Alexandru</given_name>
            <surname>Valachi</surname>
            <affiliations>
              <institution>
                <institution_name>Technical University “Gh.Asachi”Iasi, Faculty of Automatic Control and Computer Engineering, ROMANIA</institution_name>
              </institution>
            </affiliations>
          </person_name>
        </contributors>
        <jats:abstract xml:lang="en">
          <jats:p>This paper proposes a way to build digital hardware that doesn't use a global clock. Each module operates only when it has data and signals its completion directly to the next module. Instead of a single, central clock dictating when every component operates, these asynchronous systems rely on local communication, handshaking. Although both system types process binary signals, asynchronous systems differ in that timing is determined by circuit delays rather than a fixed clock cycle. From a synchronous perspective, their behavior resembles clock gating or the use of locally generated, unsynchronized clocks. In asynchronous architectures, synchronization, communication, and operation sequencing are achieved through handshake protocols between components. The use of local clocks means that registers are activated only when necessary, contributing to more efficient operation.</jats:p>
        </jats:abstract>
        <publication_date media_type="print">
          <month>12</month>
          <day>31</day>
          <year>2025</year>
        </publication_date>
        <publication_date media_type="online">
          <month>12</month>
          <day>31</day>
          <year>2025</year>
        </publication_date>
        <pages>
          <first_page>289</first_page>
        </pages>
        <publisher_item>
          <item_number item_number_type="article_number">30</item_number>
        </publisher_item>
        <ai:program name="AccessIndicators">
          <ai:license_ref>https://creativecommons.org/licenses/by/4.0/deed.en_US</ai:license_ref>
        </ai:program>
        <doi_data>
          <doi>10.37394/23201.2025.24.30</doi>
          <resource>https://wseas.com/journals/cas/2025/a605101-025(2025).pdf</resource>
        </doi_data>
        <citation_list>
          <citation key="ref0">
            <unstructured_citation>Duarte L. Oliveira; Gabriel C. Duarte; Gracieth C. Batista; Nicolly N. M. Cardoso, Converting Synchronous Digital Systems to Asynchronous Systems using Local-Clock, IEEE XXVII International Conference on Electronics, Electrical Engineering and Computing (INTERCON), Lima, Peru 2020, https://doi.org/10.1109/INTERCON50315.20 20.9220269.</unstructured_citation>
          </citation>
          <citation key="ref1">
            <unstructured_citation>Rob Aitken, IEEE VLSI Circuits and Systems Letter, Quarterly Publication of IEEE Computer Society Technical Committee on VLSI (TCVLSI), Vol.8, Issue 3, 2022, IEEE.</unstructured_citation>
          </citation>
          <citation key="ref2">
            <unstructured_citation>C.H. Van Berkel; M.B. Josephs; S.M. Nowick Applications of asynchronous circuits, Proceedings of the IEEE. pp.223-233, 2002, doi: 10.1109/5.740016.</unstructured_citation>
          </citation>
          <citation key="ref3">
            <unstructured_citation>Sparsø,Jens, Introduction to Asynchronous Circuit Design, Publication date 2020, DTU Compute, Technical University of Denmark.</unstructured_citation>
          </citation>
          <citation key="ref4">
            <unstructured_citation>Y. Nagata; M. Mukaidono, Design of an asynchronous digital system with B-ternary logic, IEEE Xplore 2002, ISBN: 0-8186- 7910-7, doi: 10.1109/ISMVL.1997.601411.</unstructured_citation>
          </citation>
          <citation key="ref5">
            <unstructured_citation>Steven Mark Nowick, Automatic Synthesis of Burst-Mode Asynchronous Controllers, Technical Report, December 1995.</unstructured_citation>
          </citation>
          <citation key="ref6">
            <unstructured_citation>Duarte L. Oliveira; Lester A. Faria; Higor A. Delsoto; Kledermon Garcia, An architecture for globally-synchronous locallyasynchronous systems on FPGAs, IEEE XXIII International Congress on Electronics, Electrical Engineering and Computing (INTERCON), Piura, Peru 2016, doi: 10.1109/INTERCON.2016.7815572.</unstructured_citation>
          </citation>
          <citation key="ref7">
            <unstructured_citation>Lukáš Nagy, Ján Koscelánsky, Viera Stopjaková, Design of a globally asynchronous locally synchronous digital system, 2014 IEEE 12th IEEE International Conference on Emerging eLearning Technologies and Applications (ICETA), Stary Smokovec, Slovakia.</unstructured_citation>
          </citation>
          <citation key="ref8">
            <unstructured_citation>J. Cortadella; A. Yakovlev; J. Garside, Logic design of asynchronous circuits, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, Bangalore, India. doi: 10.1109/ASPDAC.2002.994880.</unstructured_citation>
          </citation>
          <citation key="ref9">
            <unstructured_citation>Marcos Luiggi Lemos Sartori; Willian Analdo Nunes; Ney Laert Vilar Calazans, Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design, Published in: 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI).</unstructured_citation>
          </citation>
          <citation key="ref10">
            <unstructured_citation>Gurdeep Singh; Amanpreet Kaur, Sustainable Digital Circuit Design: Asynchronous Counter on Kintex and Virtex FPGA Platforms, 2nd International Conference on Sustainable Computing and Smart Systems (ICSCSS), Coimbatore, India, 2024.</unstructured_citation>
          </citation>
          <citation key="ref11">
            <unstructured_citation>Ovidiu Ursaru, Cristian Aghion, Mihai Lucanu, Liviu Tigaeru, Pulse width Modulation Command Systems Used for the Optimization of Three Phase Inverters, Advances in Electrical and Computer Engineering Journal. Suceava, Romania, 2009, pp.22-27.</unstructured_citation>
          </citation>
          <citation key="ref12">
            <unstructured_citation>Muhammad Kamran Bhatti; Behlol Nawaz; Abdul Majeed Soomro, Design &amp; Analysis of Asynchronous (Clockless) Circuits and Implementation using Mentor Graphics ASIC Design Tools, 2nd International Conference on Communication, Computing and Digital systems (C-CODE), 2019, Islamabad, Pakistan.</unstructured_citation>
          </citation>
          <citation key="ref13">
            <unstructured_citation>Duarte L. Oliveira;Orlando Verducci, Interfacing Synchronous Modules to MultiClock Synchronous Digital Systems Implemented in FPGA, IEEE Seventh Ecuador Technical Chapters Meeting (ECTM), 2023, https://doi.org/10.1109/ETCM58927.2023.10 309008.</unstructured_citation>
          </citation>
        </citation_list>
      </journal_article>
    </journal>
  </body>
</doi_batch>