Simulation and Analysis of Fully Adiabatic Circuit Designing with Single Power Clock for High-Frequency Low Power VLSI Circuits

888d9755-eed0-42b0-9c8d-a65996e94a6a20220531081707048wseas:wseasmdt@crossref.orgMDT DepositDESIGN, CONSTRUCTION, MAINTENANCE2732-99842944-912X10.37394/232022https://wseas.com/journals/dcm/31920223192022210.37394/232022.2022.2https://wseas.com/journals/dcm/2022.phpSimulation and Analysis of Fully Adiabatic Circuit Designing with Single Power Clock for High-Frequency Low Power VLSI CircuitsYashuSwamiDepartment of ECE, Aditya Engineering College, Surampalem, INDIAAdiabatic logic guarantees vast diminishments of power utilization since it doesn't disperse power. This paper audits ongoing advancement in adiabatic circuits. First, the fully adiabatic circuit designing technology called as pass-transistor adiabatic logic (PTAL) is discussed. Next, the operation of the dual rail logic and the power clock supply with the logic operation of the PTAL technology is discussed. Further, many basic logic circuits using the PTAL technology are designed, compiled and simulated. Finally, the performance results, power dissipation, speed, efficiency and load analysis of the circuits are compared with the conventional and existing CMOS technology under same simulation conditions using standard 45nm technology with VDD = 1V and proves that even at high frequencies above 2GHz, it is able to outperform the dominating conventional CMOS logic designing in the field of power dissipation. The simulation results are provided to support our claim. We used 45nm technology for all our simulations.5312022531202215115720https://wseas.com/journals/dcm/2022/a405117-138.pdf10.37394/232022.2022.2.20https://wseas.com/journals/dcm/2022/a405117-138.pdfShinghal D, Saxena A, Noor A. Adiabatic logic circuits: a retrospect. MIT International Journal of Electronics and Communication Engineering. 2013 Aug;3(2):108-14.. Rabaey JM, Pedram M, editors. Low power design methodologies. Springer Science & Business Media; 2012 Dec 6.. 10.1109/iscas.2001.922182B. Voss and M. Glesner, “A Low Power Sinusoidal Clock,” In Proc. of the International Symposium on Circuits & Systems, ISCAS 2001. 10.4236/cs.2016.713349Swami Y, Rai S. Comparative methodical assessment of established MOSFET threshold voltage extraction methods at 10-nm technology node. Circuits and Systems. 2016;7(13):4248. 10.1016/j.mejo.2019.104601Bhuvana BP, Bhaaskaran VK. Design of FinFET-based energy efficient pass-transistor adiabatic logic for ultra-low power applications. Microelectronics Journal. 2019 Oct 1;92:104601.. 10.1007/s12633-018-9984-zSwami Y, Rai S. Ultra-thin high-K dielectric profile based NBTI compact model for nanoscale bulk MOSFET. Silicon. 2019 Jun;11(3):1661-71. 10.1109/lpe.1994.573221T. Indermauer and M. Horowitz, “Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power Design,” Technical Digest IEEE Symposium Low Power Electronics, 102-103, Oct’ 02. 10.1016/j.spmi.2016.12.044Swami Y, Rai S. Modeling and analysis of subsurface leakage current in nano-MOSFET under cutoff regime. Superlattices and Microstructures. 2017 Feb 1;102:259-72. 10.1109/tvlsi.2004.836320A. Blotti and R. Saletti, “Ultralow- Power Adiabatic Circuit Semi-Custom Design,” IEEE Transactions on VLSI Systems, vol.12, 1248-53, Nov’ 04. 10.1109/mwscas.2005.1594372Hu J, Xu T, Xia Y. Low-power adiabatic sequential circuits with complementary passtransistor logic. In48th Midwest Symposium on Circuits and Systems, 2005. 2005 Aug 7 (pp. 1398-1401). IEEE. 10.1007/s12633-020-00436-yKumar A, Swami Y, Rai S. Modeling of surface potential and fringe capacitance of selective buried oxide junctionless transistor. Silicon. 2021 Feb;13(2):389-97. Roy K, Prasad SC. Low-power CMOS VLSI circuit design. John Wiley & Sons; 2009 Feb 2. MOSIS: MOS Integration Service. Available online: www.mosis.org. 10.11648/j.ajmp.20180704.14Swami Y, Rai S. Modeling and characterization of inconsistent behavior of gate leakage current with threshold voltage for Nano MOSFETs. American Journal of Modern Physics. 2018;7(4):166-72. C. HU, “Future CMOS Scaling and Reliability,” Proceedings IEEE, Vol. 81, No. 05, pp. 682-689, February 2004. 10.1166/jno.2019.2443Swami Y, Rai S. Comprehending and Analyzing the Quasi-Ballistic Transport in Ultra Slim Nano-MOSFET Through Conventional Scattering Model. Journal of Nanoelectronics and Optoelectronics. 2019 Jan 1;14(1):80-91.