Abstract: This research study aims to understand the variation of power dissipation according to the variation of power clock provided to Efficient Charge Recovery Logic, Positive Feedback Adiabatic Logic, 2N-N-2P, and 2N-2N-2P Adiabatic logic families. This study aims to understand how varying the parameters of the power clock affects the adiabatic circuit’s power consumption and the output signal integrity. The paper considers the NAND gate as a bench-marking circuit to gather data for this study by implementing it in the considered logic families. The input power clock’s frequency ranges from 100 MHz to 1 GHz. This study is particular to the scenario of Ultra Low Supply Voltage of the power clock hence the decided range for analysis of the voltage is 0.3V ≤ $$V_{dd}$$ ≤ 0.6V and industrially popular 1V. The final result sums up the performance of all 4 adiabatic logic families considered above and identifies Positive Feedback Adiabatic Logic as the most power-saving family overall and 2N-N-2P Adiabatic Family as the most immune to frequency variation. The general trend is also observed to be disrupted for 0.3V and 0.4V as 2N-N-2P unexpectedly consumes less power than 2N-2N-2P. A similar change of trend in 0.5 and 0.6, where Efficient charge Recovery Logic performs better than 2N-N-2P and 2N-2N-2P, and in 1V, it outperforms all other techniques.

Keywords: ECRL, PFAL, 2N-N-2P, 2N-2N-2P, Adiabatic Logic Techniques, Low Power Circuits

Pages: 134-142