Published Articles with Keyword: Adder
- Title: Design of an Efficient Single Precision Floating Point Unit
Authors: Vasudeva G, Bharathi Gururaj
Doi: 10.37394/232027.2025.7.5
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Published in International Journal of Electrical Engineering and Computer Science, Volume 7, 2025
- Title: Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design
Authors: Venkata Rao Tirumalasetty, K. Babulu, G. Appala Naidu
Doi: 10.37394/23202.2024.23.16
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Published in WSEAS Transactions on Systems, Volume 23, 2024
- Title: FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder
Authors: G. Erna, G. Srihari, M. Purna Kishore, Ashok Nayak B., M. Bharathi
Doi: 10.37394/23201.2023.22.13
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Published in WSEAS Transactions on Circuits and Systems, Volume 22, 2023
- Title: Designing a Histological Analyzer for Diagnosing Pathomorphological Changes in Tissues as an Example of Chlamydial Infection
Authors: Sergey Kostarev, Rustam Fayzrakhmanov, Nataliya Tatarnikova, Oksana Novikova, Tatyana Sereda
Doi: 10.37394/23209.2023.20.18
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Published in WSEAS Transactions on Information Science and Applications, Volume 20, 2023
- Title: Design and Performance Analysis of Memristor and IMPLY Adder based 64-bit Vedic Multiplier and CAM Memory with Gbps throughput on FPGA
Authors: Shruthi K. N., R. Bhagyalakshmi, Roopashree D.
Doi: 10.37394/23203.2022.17.41
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Published in WSEAS Transactions on Systems and Control, Volume 17, 2022
- Title: Comparison of Statistical Methods for Claims Reserve Estimation Using R Language
Authors: Endri Raço, Kleida Haxhi, Etleva Llagami, Oriana Zaçaj
Doi: 10.37394/23206.2022.21.61
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Published in WSEAS Transactions on Mathematics, Volume 21, 2022
- Title: Design and FPGA Implementation of High Throughput and Low Latency Machine Learning based Approximate Multiplier for Image Processing Applications
Authors: Anil Kumar D.
Doi: 10.37394/23203.2022.17.33
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Published in WSEAS Transactions on Systems and Control, Volume 17, 2022
- Title: Investigation on Power, Delay and Area optimization of XOR Gate
Authors: Thamizharasan. V, Ramya. M
Doi: 10.37394/23201.2020.19.32
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Published in WSEAS Transactions on Circuits and Systems, Volume 19, 2020
- Title: Triple-Mode Floating-Point Adder Architectures
Authors: Liu De, Wang Mingjiang
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Published in WSEAS Transactions on Electronics, Volume 9, 2018
- Title: VLSI Implementation of Lattice Wave Digital Filters for Increased Sampling Rate Using Three Port Parallel Adaptors
Authors: Meenakshi Agarwal, Tarun Kumar Rawat
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Published in WSEAS Transactions on Circuits and Systems, Volume 17, 2018
- Title: Design of Power Efficient Digital Systems Using Adiabatic Techniques
Authors: G. Sambasiva Rao, Pattan Vaseem Ali Khan
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Published in WSEAS Transactions on Circuits and Systems, Volume 16, 2017
- Title: Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding
Authors: P. Balasubramanian, K. Prasad
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Published in WSEAS Transactions on Circuits and Systems, Volume 16, 2017
- Title: Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit
Authors: P. Balasubramanian, N. E. Mastorakis
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Published in WSEAS Transactions on Circuits and Systems, Volume 15, 2016
- Title: An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder
Authors: P. Balasubramanian, N. E. Mastorakis
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Published in WSEAS Transactions on Circuits and Systems, Volume 15, 2016
- Title: Low Power Heterogeneous Adder
Authors: Karthick S, Valarmathy S, Prabhu E
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Published in WSEAS Transactions on Circuits and Systems, Volume 14, 2015
- Title: Synthesis of Adder Circuit Using Cartesian Genetic Programming
Authors: S. Asha, R. Rani Hemamalini
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Published in WSEAS Transactions on Circuits and Systems, Volume 14, 2015
- Title: A 12-bit CMOS Dual-Ladder Resistor String D/A Converter Integrated with Self-adjusted Reference Circuit
Authors: Feng Yang, Chaoqun An, Liang Xie, Xiangliang Jin
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Published in WSEAS Transactions on Circuits and Systems, Volume 13, 2014
- Title: A High Performance Pipelined Discrete Hilbert Transform Processor
Authors: Wang Xu, Zhang Yan, Ding Shunying
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Published in WSEAS Transactions on Signal Processing, Volume 9, 2013
- Title: Hardware Modeling of Binary Coded Decimal Adder in FPGA
Authors: Muhammad Ibn Ibrahimy, Md. Rezwanul Ahsan, Iksannurazmi B. Bambang Soeroso
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Published in WSEAS Transactions on Computers, Volume 11, 2012
- Title: A Configurable Floating-Point Discrete Hilbert Transform Processor for Accelerating the Calculation of Filter in Katsevich Formula
Authors: Wang Xu, Zhang Yan, Wang Fei, Ding Shunying
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Published in WSEAS Transactions on Communications, Volume 11, 2012
- Title: Design of Low Power Full Adder Using Active Level Driving Circuit
Authors: K. N. Vijeyakumar, V. Sumathy, M. Nithya, C. Venkatnarayanan, V. Thiruchitrabala
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Published in WSEAS Transactions on Circuits and Systems, Volume 11, 2012