Abstract: This paper proposes a way to build digital hardware that doesn't use a global clock. Each module operates only when it has data and signals its completion directly to the next module. Instead of a single, central clock dictating when every component operates, these asynchronous systems rely on local communication, handshaking. Although both system types process binary signals, asynchronous systems differ in that timing is determined by circuit delays rather than a fixed clock cycle. From a synchronous perspective, their behavior resembles clock gating or the use of locally generated, unsynchronized clocks. In asynchronous architectures, synchronization, communication, and operation sequencing are achieved through handshake protocols between components. The use of local clocks means that registers are activated only when necessary, contributing to more efficient operation.

Keywords: Locally Clock, Asynchronous Digital Clock, FPGA, Latch, Verilog HDL, Demo Board

Pages: 289-297